Direct Memory Access
CPU may transfer data to or from a number of external (other than memory) devices. The operation
treated the I/O system for reading and writing in the same manner as memory, using address, data lines and WR
RD control lines. This requires CPU intervention and is costly in "time".
Direct Memory Access--the ability of an I/O subsystem to transfer data to and from a memory subsystem without
processor intervention.
DMA Controller--a device that can control data transfers between an I/O subsystem and a memory subsystem in the
same manner that a processor can control such transfers.
Functional behaviour of a DMA transaction
1. The processor transmits the following information to a DMA controller:
(a) beginning address in memory
(b) block length (number of words to transfer)
(c) direction (memory-to-device or device-to-memory)
(d) port ID
(e) end of block action (interrupt request or no interrupt request).
2. The processor returns to other activities while the DMA controller starts the data transfer.
3. Each time the DMA controller accesses memory, it synchronises this memory request with an idle period of the
processor--to do this the possibilities are:
(a) force an immediate disabling of the processor, or
(b) request a halt of the processor, and await an acknowledgement, or
(c) time the DMA access to a clock interval or status signal of the processor that signals an idle cycle.
4. When the DMA controller accesses an I/O port or memory, it uses the same functional control signals as used by
the processor. I/O port activity can be performed on dedicated lines that do not have to be synchronised with the
processor.
5. At the completion of the block transfer, the DMA controller raises an interrupt request if the interrupts are
"armed" and otherwise indicates completion in its status register.
6. The processor recognises I/O completion (either by interrupt or by reading the status register); thereafter the
activity between the processor and the DMA controller follows the normal post-completion activity of any I/O port.
CPU may transfer data to or from a number of external (other than memory) devices. The operation
treated the I/O system for reading and writing in the same manner as memory, using address, data lines and WR
RD control lines. This requires CPU intervention and is costly in "time".
Direct Memory Access--the ability of an I/O subsystem to transfer data to and from a memory subsystem without
processor intervention.
DMA Controller--a device that can control data transfers between an I/O subsystem and a memory subsystem in the
same manner that a processor can control such transfers.
Functional behaviour of a DMA transaction
1. The processor transmits the following information to a DMA controller:
(a) beginning address in memory
(b) block length (number of words to transfer)
(c) direction (memory-to-device or device-to-memory)
(d) port ID
(e) end of block action (interrupt request or no interrupt request).
2. The processor returns to other activities while the DMA controller starts the data transfer.
3. Each time the DMA controller accesses memory, it synchronises this memory request with an idle period of the
processor--to do this the possibilities are:
(a) force an immediate disabling of the processor, or
(b) request a halt of the processor, and await an acknowledgement, or
(c) time the DMA access to a clock interval or status signal of the processor that signals an idle cycle.
4. When the DMA controller accesses an I/O port or memory, it uses the same functional control signals as used by
the processor. I/O port activity can be performed on dedicated lines that do not have to be synchronised with the
processor.
5. At the completion of the block transfer, the DMA controller raises an interrupt request if the interrupts are
"armed" and otherwise indicates completion in its status register.
6. The processor recognises I/O completion (either by interrupt or by reading the status register); thereafter the
activity between the processor and the DMA controller follows the normal post-completion activity of any I/O port.
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